Programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), typically include input/output blocks (IOBs) for providing and receiving external data. The IOBs of some PLDs can be configured to implement a low voltage differential signal (LVDS) scheme using an LVDS input buffer and an LVDS output buffer.
FIG. 1 is a block diagram of a conventional IOB 100 that includes both an LVDS output buffer 101 and an LVDS input buffer 102. After the PLD has been configured, either LVDS output buffer 101 or LVDS input buffer 102 can be enabled such that the enabled buffer is effectively coupled to differential communication channel 140.
Parasitic resistances 121–124 are located in the path between IOB 100 and communications channel 140. The chip boundary of the associated PLD is illustrated by dashed line 150. Thus, parasitic resistances 121–122 are on-chip resistances that exist between the output terminals of output driver 101, the input terminal of input driver 102 and the chip boundary. These on-chip parasitic resistances 121–122 are largely represented by the conductive elements required to couple IOB 100 to the pad of the chip, and the conductive elements (e.g., bonding wires or solder balls) required to couple the pin of the chip to a contact element on the external structure of the package. Parasitic resistances 123–124 are off-chip resistances that exist between pins of the chip and termination resistor 130. Parasitic resistances 123–124 typically represent traces on a printed circuit board. Although termination resistor 130 is typically located as close as possible to the pins of the receiving chip, the parasitic resistances 123–124 will always exist.
LVDS output buffer 101 includes an LVDS transmitter 110, which provides a differential output signal to communications channel 140 in response to an output data value DOUT. An internal termination resistance 111 is provided within the LVDS transmitter 110. The internal termination resistance 111 is designed to provide for proper signal termination at the transmit end of communication channel 140. Thus, when IOB 100 is configured as an LVDS transmitter, the internal termination resistance 111 provides proper signal termination at the transmit side of communication channel 140, without requiring a termination resistor external to the PLD.
LVDS input buffer 102 includes an LVDS receiver 120, which provides an input data value DIN in response to a differential input signal received on communications channel 140. LVDS receiver 120 does not include an internal termination resistance. As a result, an external termination resistance 130 must be provided across the lines of differential communications channel 140 when IOB 100 is configured as an LVDS receiver. This external termination resistance 130 is selected to provide the proper signal termination at the receive side of communication channel 140. Parasitic resistances 121–124 are located between termination resistor 130 and the input terminals of LVDS receiver 120. These parasitic resistances can cause signal degradation, causing LVDS receiver 120 to provide erroneous input data values DIN.
It would therefore be desirable to have an improved IOB, which allows an LVDS receiver to be terminated in a manner that substantially eliminates the parasitic resistances between the input terminals of the LVDS receiver and the termination resistance. It would further be desirable to have an improved IOB, which provides an internal termination resistance for an LVDS receiver. It would further be desirable for such an improved IOB to be implemented in a manner consistent with present IOBs.